1. Field of the Invention
The present invention relates to a semiconductor memory for relieving a defective bit, and more particularly to a semiconductor memory for relieving a defective bit without forming a redundant cell array for relieving a defective bit.
2. Description of the Related Art
A large capacity semiconductor memory has a configuration to relieve a defective bit for improving yield and decreasing price. Specifically a semiconductor memory has a redundant cell array which can replace a defective word or defective column containing a defective bit, in addition to a regular cell array. And if a defective bit is detected in the regular cell array at the operation test, the defective word line or defective column line containing the defective bit is replaced with the word line or column line in the redundant cell array. And the address of the defective bit is stored in the ROM in order to replace the defective bit with the redundant cell. Then it is checked whether the access target address matches with the address of the defective bit in the regular operation, and if a match, the redundant cell is accessed in addition to accessing the defective cell, and the output of the redundant cell is selected and the data of the redundant cell is output. By this, the yield of the semiconductor memory can be improved. This redundant cell array configuration is used not only for DRAM but also for various memories, such as FeRAM and SRAM.
A semiconductor memory having the above mentioned redundant cell array is disclosed in Japanese Patent Application Laid-Open No. S57-64395 and No. 2002-298596, for example.